In some double-data rate (DDR) memory systems, command busses are trained using a link training procedure on power-on of the system to align the command slots targeting specific memory channels. For example, as shown in FIG. 1, during link training, commands (CMDA) on the memory bus (VCMD) targeting a first DDR channel may be trained for a first slot (slot A), while commands (CMDB) targeting a second DDR channel may be trained for a second slot (slot B).
To save power in some DDR memory systems, a memory command clock (VCK) and any high speed logic associated with the paths using the memory command clock may be shut down, while the core clock (CCLK) continues to run. On resuming the memory command clock, any first-in, first-out (FIFO) storage components on the memory command clock must be started with the same read/write pointer separation as before entering clock stop. After exiting clock stop and resuming the memory command clock, however, the command slots may no longer be aligned—a command issued for a first slot could be in the second slot, and vice versa. This non-determinism may result in a failure, requiring a re-training of the link, which may negatively impact system performance and clock stop exit time requirements.